This invention relates to a sample and hold circuit for sampling a high frequency signal, for example, a video signal.
Pulse code modulation (PCM) is now primarily used for the transmission of the video signal. In the PCM transmission, the video signal is sampled, quantitized, and coded. To sample a signal such as a video signal at high frequencies, a high speed sample and hold circuit is required.
FIG. 1 shows a conventional high speed sample and hold circuit. The sample and hold circuit is provided with a capacitor 10 and a bridge circuit 12 for charging and discharging the capacitor 10. The bridge circuit 12 contains NPN transistors Q1 to Q4 of which the bases are connected to the collectors, respectively. A signal source 14 is connected to a junction of the emitter of the transistor Q1 and the collector of the transistor Q2. A junction between the emitter of the transistor Q3 and the collector of the transistor Q4 is connected to the capacitor 10. A constant voltage supply 16 is connected through a constant current source 18 to the collectors of the transistors Q1 and 03. The emitters of the transistors Q2 and Q4 are grounded through the constant current source 20. The sample and hold circuit includes a pulse generator 22 for periodically generating first and second control pulses from first and second control terminals, and further includes NPN transistors Q5 and Q6. The first control pulse has an inverted relation to the second control pulse. The voltage at the first control terminal changes from a low to high level when the voltage at the second control terminal changes from high to low. The bases of the NPN transistors Q5 and Q6 are connected to the respective collectors of these transistors. With such a connection, those transistors serve as diodes. The first terminal of the pulse generator 22 is connected to the emitter of the NPN transistor Q5. The collector of the NPN transistor Q5 is connected to the collectors of the NPN transistors Q1 and Q3. The second control terminal of the pulse generator 22 is connected to the collector of the NPN transistor Q6. The emitter of the NPN transistor Q6 is connected to the emitters of the NPN transistors Q2 and Q4.
In this sample and hold circuit, when the level of the voltages V1 and V2 at the first and second control terminals of the pulse generator 22 are low and high, respectively, the voltage of the input signal is held. When the voltages V1 and V2 are high and low, respectively, the input signal voltage is sampled.
When the sample and hold circuit is in a holding mode, for example, a constant current I1 derived from a constant current circuit 18 flows into the first control terminal of the pulse generator 22 through the NPN transistor Q5. On the other hand, a constant current I2 is fed from the second control terminal of the pulse generator 22 into a constant current source 20. At this time, the transistors Q3 and Q4 are nonconductive. Accordingly, the voltage across the capacitor 10 is kept constant without regard to the input signal VIN.
A relationship between the input signal VIN and the output signal VOUT will be described referring to FIG. 2. The output signal VOUT corresponds to the voltage VC1 across the capacitor 10. In FIG. 2, VX designates a voltage difference between the input signal VIN and the output signal VOUT. In FIG. 2, the voltages V1 and V2 at the first and second terminals of the pulse generator 22 are inverted at time To. When the voltage V1 increases above the voltage VC1 across the capacitor 10 and, moreover, the voltage V2 drops below the input signal VIN, the transistors Q5 and Q6 prohibit the current from flowing through the transistors per se. As a result, the constant current I1 from the constant current source 18 flows through the NPN transistor Q3. At the same time, the constant current I2 is supplied from the signal source 14 to the constant current source 20 through the NPN transistor Q2. At this time, no current flows into the transistors Q1 and Q4. Therefore, the capacitor 10 is charged by the constant current I1 irrespective of the input signal VIN, i.e., voltage from the signal source 14. Through this charging, the voltage across the capacitor 10 increases at a fixed rate.
The voltage difference VX becomes smaller than a predetermined threshold voltage V.phi. of the bridge circuit 12 at time T2. At this time, the transistors Q1 and Q4 are both conductive, and the capacitor 10 is charged by a nonlinearly changing current. A change of current corresponds to a time constant as determined by the capacitance of the capacitor 10 and the impedance of the bridge circuit 12. In FIG. 2, TC1 designates a charge/discharge time by the constant current; TC2, a charge/discharge time by the current as defined by the time-constant.
As described above, the two types of modes are present in the charge/discharge of the capacitor 10. For this reason, the conventional sample and hold circuit is unsatisfactory in reliability when it operates in a high speed operation. Specifically, in the sample and hold circuit, when an amplitude of the input signal VIN is large, the constant currents I1 and I2 must be set at large values. Otherwise, it takes a long time for the output signal VOUT to reach the input signal. As a result, the response characteristic is poor. In this condition, it is very difficult to sample a signal such as the video signal in the high frequency band.